kw.\*:("Layout plan")
Results 1 to 25 of 398
Selection :
Génération automatique de plans de masse = Automatic generation of layout plansKOUKA, E. F.TSI. Technique et science informatiques. 1989, Vol 8, Num 6, pp 557-569, issn 0752-4072, 13 p., no specArticle
New heuristic for the dynamic layout problemEREL, E; GHOSH, J. B; SIMON, J. T et al.The Journal of the Operational Research Society. 2003, Vol 54, Num 12, pp 1275-1282, issn 0160-5682, 8 p.Article
High voltage microwave DC block for microstrip ground planesKOSCICA, T. E.Electronics Letters. 1990, Vol 26, Num 16, pp 1287-1288, issn 0013-5194Article
New clustering approach to chip floorplan using functional dataHARADA, I; ADACHI, T.Electronics Letters. 1987, Vol 23, Num 17, pp 900-902, issn 0013-5194Article
Enumerating floorplans with n roomsNAKANO, Shin-Ichi.Lecture notes in computer science. 2001, pp 107-115, issn 0302-9743, isbn 3-540-42985-9Conference Paper
A new placement method for direct mapping into LUT-based FPGAsABKE, Joerg; BARKE, Erich.Lecture notes in computer science. 2001, pp 27-36, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Tightly integrated placement and routing for FPGAsKANNAN, Parivallal; BHATIA, Dinesh.Lecture notes in computer science. 2001, pp 233-242, issn 0302-9743, isbn 3-540-42499-7Conference Paper
A new heuristic algorithm for rectangle packingWENQI HUANG; DUANBING CHEN; RUCHU XU et al.Computers & operations research. 2007, Vol 34, Num 11, pp 3270-3280, issn 0305-0548, 11 p.Article
A Generic Library for Adaptive Computing EnvironmentsNEUMANN, Tilman; KOCH, Andreas.Lecture notes in computer science. 2001, pp 503-512, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Conception de haut niveau de circuits intégrés: Prise en compte des problèmes liés aux interconnexions = High level integrated circuit design: interconnection problems taken into accountCHILLET, Daniel; YU, Raofeng; DUBOIS, Hélène et al.Workshop AAA sur l'adéquation algorithme architecture. 2000, pp 7-14Conference Paper
Methods and effects of introduction of the functional component grouping process into systematizationTANIGUCHI, K.JSME international journal. Series C, dynamics, control, robotics, design and manufacturing. 1996, Vol 39, Num 3, pp 660-666, issn 1340-8062Article
Noncrossing subgraphs in topological layoutsKRATOCHVIL, J; LUBIW, A; NESETRIL, J et al.SIAM journal on discrete mathematics (Print). 1991, Vol 4, Num 2, pp 223-244, issn 0895-4801Article
Optimal chaining of CMOS transistors in a functional cellWIMER, S; PINTER, R. Y; FELDMAN, J. A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1987, Vol 6, Num 5, pp 795-801, issn 0278-0070Article
Canonical decomposition, realizer, Schnyder labeling and orderly spanning trees of plane graphs: (Extended abstract)MIURA, Kazuyuki; AZUMA, Machiko; NISHIZEKI, Takao et al.Lecture notes in computer science. 2004, pp 309-318, issn 0302-9743, isbn 3-540-22856-X, 10 p.Conference Paper
An automated method for overlay sample plan optimization based on spatial variation modelingXUEMEI CHEN; PREIL, Moshe E; LE GOFF-DUSSABLE, Mathilde et al.SPIE proceedings series. 2001, pp 257-266, isbn 0-8194-4030-2Conference Paper
ITER generic site layout and servicesAHLFELD, C; CHUYANOV, V; DILLING, D et al.SOFT : Symposium on fusion technology. 1998, 2Vol, Vol 2, 1689-1692Conference Paper
APPROCHE MULTICRITERE POUR L'AIDE AU CHOIX D'UNE SOLUTION DE PLAN MASSE BATIMENT = MULTICRITERIA APPROACH ALLOWING TO CHOOSE A SOLUTION OF BUILDING LAYOUT PLANZatar, Abdallah; Boissier, Daniel.1997, 182 p.Thesis
ALSO: a system for chip floorplan designHSU, Y. C; KUBITZ, W. J.Integration (Amsterdam). 1988, Vol 6, Num 2, pp 127-146, issn 0167-9260Article
Placing, routing, and editing virtual FPGAsLAGADEC, Loïc; LAVENIER, Dominique; FABIANI, Erwan et al.Lecture notes in computer science. 2001, pp 357-366, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Höherer Störabstand für Embedded-Systeme = Always less perturbations for embedded systemsBAKER, B. C.Embedded engineering. 2000, Num 1, pp 29-32, issn 1616-3370Article
Knowledge-based approach to overall configuration of multistory office buildings = Méthode par base de connaissances pour la conception générale de bâtiments de bureau élevésBEDARD, C; RAVI, M.Journal of computing in civil engineering. 1991, Vol 5, Num 4, pp 336-353, issn 0887-3801Article
A logic-to-logic comparator for VLSI layout verificationMAURER, P. M; SCHAPIRA, A. D.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 8, pp 897-907, issn 0278-0070Article
Linear placement algorithms and applications to VLSI designCHUNG-KUAN CHENG.Networks (New York, NY). 1987, Vol 17, Num 4, pp 439-464, issn 0028-3045Article
Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article
Óbidos : Un complexe touristique haut en architecture = Óbidos: A tourist complex rich in architectureALBERT, Marie-Douce.Le Moniteur des travaux publics et du bâtiment. 2012, Num NOV, pp 30-31, issn 0026-9700, 2 p., NSArticle